Semiconductor technologies continue to evolve. Computing and communications designs are incorporating more functionality, higher processing and transmission speeds, smaller sizes, more memory, etc., into smaller and more robust architectures. These trends have placed particular demands on interconnect architectures.
Semiconductor memories are advancing in many ways. Memory devices have increased capacities, increased operating frequencies, reduced latencies, etc., all while ramping with the exponential density increases according to Moore's Law.
To improve memory IO capability, high-speed serial links can be used to couple memories with memory controllers. Unfortunately, these links operate at speeds that are not testable in a cost effective manner on conventional equipment such as automatic test equipment (ATE), burn in ovens or other test hardware.
Conventional DRAMs have single ended interfaces that are tested at speed on automatic test equipment (ATE). As DRAM speeds increase this test method becomes increasingly difficult and costly. This equipment is currently capable of testing memory up to 1067 MHz. Future DRAM interfaces are expected to operate at 3.2 GHz and above, which may require testers that are considerably faster and more costly.
One way to address this problem is to incorporate on-die circuitry for IO self-test. On-die pattern generator and checker circuits have been proposed in the past for testing of high-speed logic chips. One example of this is an interconnect built in self test (IBIST), which is an emerging standard for testing of high-speed connections for logic chips. Unlike logic chips, memory chips have limitations on the number of gates that can be cost-effectively integrated on a die.